Conventionally, the demand for size reduction of a semiconductor device has increased along with the progress in manufacturing technology of the semiconductor device. One of technologies for meeting the demand for size reduction of the semiconductor device is a wafer level packaging technology. In the wafer level packaging technology, a semiconductor substrate where semiconductor elements have been formed at a wafer level is subjected to formation of wirings and electrodes at the wafer level, and then a surface of the semiconductor substrate is sealed with a predetermined cover and cut into a chip size through dicing, thereby providing individual semiconductor devices.
In the wafer level packaging technology, wirings formed on both main surfaces of the semiconductor substrate are connected to each other by a through silicon via (TSV) with which a through hole provided for the semiconductor substrate is filled. In the formation of the through hole, pressure applied to the wiring formed on the surface of the semiconductor substrate might result in a trouble of wiring separation or breakage.